Miscellaneous Bibliography Items

Some reconfigurable computing related bibliography entries. These are found in my Ph.D. dissertation Programming Fine-Grained Reconfigurable Architectues, The University of Texas at Austin, 1995.

Steven Guccione / guccione@NOSPAM.io.com

[Aho et al., 1974]
Alfred V. Aho, John E. Hopcroft, and Jeffrey D. Ullman. The Design and Analysis of Computer Algorithms. Addison-Wesley Publishing Company, 1974.

[Aho et al., 1986]
Alfred V. Aho, Ravi Sethi, and Jeffrey D. Ullman. Compilers: Principles, Techniques and Tools. Addison-Wesley Publishing Company, 1986.

[Alamasi and Gottlieb, 1989]
George S. Alamasi and Alan Gottlieb. Highly Parallel Computing. The Benjamin/Cummings Publishing Company, Inc., 1989.

[Alg, 1990]
Algotronix, Ltd. CAL1024 Datasheet, 1990.

[Arvind and Iannucci, 1983]
Arvind and Robert A. Iannucci. A critique of multiprocessing von Neumann style. In Proceedings, 10th International Symposium on Computer Architecture, pages 426-436, 1983.

[Arvind et al., 1988]
Arvind, David E. Culler, and Gino K. Maa. Assessing the benefits of fine-grain parallelism in dataflow programs. In Supercomputing '88, pages 60-69, 1988.

[Athanas and Silverman, 1993]
Peter M. Athanas and Harvey F. Silverman. Processor reconfiguration through instruction-set metamorphosis. IEEE Computer, 26(3):11-18, March 1993.

[Athanas, 1992a]
Peter M. Athanas. A a adaptive machine architecture and compiler for dynamic processor reconfiguration. Technical Report LEMS-101, Brown University, Division of Engineering, February 1992.

[Athanas, 1992b]
Peter M. Athanas. A functional reconfigurable architecture and compiler. Technical Report LEMS-100, Brown University, Division of Engineering, February 1992.

[Backus, 1978]
J. Backus. Can programming be liberated from the von Neumann style? a functional style and its algebra of programs. Communications of the ACM, 21(8):613-641, August 1978. 1977 ACM Turing Award Lecture.

[Baker, 1993]
Stan Baker. Logical shift in the paradigm. Electronic Engineering Times, page 35, August 23 1993.

[Bertin et al., 1989]
Patrice Bertin, Didier Roncin, and Jean Vuillemin. Introduction to programmable active memories. Technical Report 3, DEC Paris Research Laboratory, 1989.

[Bertin et al., 1993]
Patrice Bertin, Didier Roncin, and Jean Vuillemin. Programmable active memories: A performance assessment. Technical Report 24, DEC Paris Research Laboratory, 1993.

[Blelloch, 1987]
Guy Blelloch. Scans as primitive parallel operations. In Proceedings of the 1987 International Conference on Parallel Processing, pages 355-3672, 1987.

[Blelloch, 1990]
Guy E. Blelloch. Vector Models for Data-Parallel Computing. The MIT Press, Cambridge, MA, 1990.

[Borkar et al., 1988]
Shekhar Borkar, Robert Cohn, George Cox, Sha Gleason, Thomas Gross, H. T. Kung, Monica Lam, Brian Moore, Craig Peterson, John Pieper, Linda Rankin, P.S. Tseng, Jim Sutton, John Urbanski, and Jon Webb. iWarp: An integrated solution to high-speed parallel computing. In Supercomputing '88, pages 330-339, 1988.

[Brunvand and Sproull, 1989]
Erik Brunvand and Robert F. Sproull. Translating concurrent programs into delay insensitive circuits. In ICCAD-89, pages 262-265, November 1989.

[Butler et al., 1991]
Michael Butler, Tse-Yu Yeh, Yale Patt, Mitch Alsup, Hunter Scales, and Michael Shebanow. Single instruction stream parallelism is greater then two. In International Symposium on Computer Architecture, pages 276-286, 1991.

[Carter et al., 1986]
William S. Carter, Khue Duong, Ross Freeman, Hung-Cheng Hseih, Jason Y. Ja, John E. Mahoney, Luan T. Ngo, and Shelly L. Sze. A user programmable reconfigurable logic array. In IEEE 1986 Custom Integrated Circuits Conference, pages 233-235, 1986.

[Chan et al., 1992]
Pak K. Chan, Martine D. F. Schlag, and Marcelo Martin. BORG: A reconfigurable prototyping board using field-programmable gate arrays. In First International ACM/SIGDA Workshop on Field Programmable Gate Arrays, pages 47-51, 1992.

[Comerford and Watson, 1992]
Richard Comerford and George F. Watson. Memory catches up. IEEE Spectrum, 29(10):34-35, October 1992.

[Cox and Blanz, 1992]
Charles E. Cox and W. Ekkehard Blanz. GANGLION -- a fast field-programmable gate array implementation of a connectionist classifier. IEEE Journal of Solid-State Circuits, 27(3):288-299, March 1992.

[Cybenko and Kuck, 1992]
George Cybenko and David J. Kuck. Revolution or evolution. IEEE Spectrum, 29(9):39-41, September 1992.

[den Bout et al., 1992]
David E. Van den Bout, Joseph H. Morris, Douglas Thomae, Scott Labrozzi, Scot Wingo, and Dean Hallman. AnyBoard: An FPGA-based reconfigurable system. IEEE Design and Test of Computers, 9(3):21-30, September 1992.

[den Bout, 1993]
David E. Van den Bout. The anyboard: Programming and enhancements. In IEEE Workshop on FPGAs for Custom Computing Machines, pages 68-77, 1993.

[Dennis and Rong, 1983]
Jack B. Dennis and Gao Guang Rong. Maximum pipelining of array operations on static data flow machine. In International Conference on Parallel Processing, pages 331-334, August 1983.

[Dennis, 1980]
Jack B. Dennis. Data flow supercomputers. IEEE Computer, 13:48-56, November 1980.

[Ebeling et al., 1991]
Carl Ebeling, Gaetino Borriello, Scott A. Hauck, David Song, and Elizabeth A. Walkup. TRIPTYCH: A new FPGA architecture. In Will Moore and Wayne Luk, editors, FPGAs, pages 75-90. Abingdon EE&CS Books, 1991.

[Ellis and Stroustrup, 1990]
Margaret A. Ellis and Bjarne Stroustrup. The Annotated C++ Reference Manual. The Addison-Wesley Publishing Company, 1990.

[Estrin and Turn, 1963]
Gerald Estrin and R. Turn. Automatic assignment of computations in a variable structure computer system. IEEE Transactions on Electronic Computers, EC-12(5):755-773, December 1963.

[Estrin and Viswanathan, 1962]
Gerald Estrin and C. R. Viswanathan. Organization of a ``fixed-plus-variable'' structure computer for eigenvalues and eigenvectors of real symmetric matricies. Journal of the ACM, 9(1):41-60, January 1962.

[Estrin et al., 1963]
Gerald Estrin, B. Bussell, R. Turn, and J. Bibb. Parallel processing in a restructurable computer system. IEEE Transactions on Electronic Computers, EC-12(5):747-755, December 1963.

[Estrin, 1960]
Gerald Estrin. Organization of computer systems -- the fixed plus variable structure computer. In Proceedings of the Western Joint Computer Conference, pages 33-40, May 1960.

[Fagin and Renard, 1994]
Barry Fagin and Cyril Renard. Field programmable gate arrays and floating point arithmetic. IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, 2(3):365-367, September 1994.

[Feo, 1988]
John T. Feo. An analysis of the computational and parallel complexity of the livermore loops. Parallel Computing, 7(2):163-185, June 1988.

[Fischer et al., 1983]
Allan L. Fischer, H. T. Kung, Louis M. Monier, and Hank Walker. Design of the PSC: A programmable systolic chip. In Randal Bryant, editor, Third Caltech Conference on Very Large Scale Integration, pages 287-302. Computer Science Press, 1983.

[Fleisher and Maissel, 1975]
H. Fleisher and L. I Maissel. An introduction to array logic. IBM Journal of Research and Development, pages 98-109, March 1975.

[Floyd, 1979]
Robert W. Floyd. The paradigms of programming. Communications of the ACM, 22(8):455-460, August 1979. 1979 ACM Turing Award Lecture.

[Freeman, 1988]
Ross Freeman. User-programmable gate arrays. IEEE Spectrum, 25(12):32-35, December 1988.

[Furtek et al., 1990]
Fredrick Furtek, Glen Stone, and Ian Jones. Labyrinth: A homogeneous computational medium. In IEEE Custom Integrated Circuits Conference, pages 31.1.1-31.1.4, 1990.

[Gajski et al., 1982]
D. D. Gajski, D. A. Padua, D. J. Kuck, and R. H. Kuhn. A second opinion on data flow machines and languages. IEEE Computer, 15:58-69, February 1982.

[Gajski, 1981]
Daniel D. Gajski. An algorithm for solving linear recurrence systems on parallel and pipelined machines. IEEE Transactions on Computers, C-30:190-206, March 1981.

[Gao, 1989]
Guang R. Gao. Algorithmic aspects of balancing techniques for pipelined data flow code generation. Journal of Parallel and Distributed Computing, 6:39-61, 1989.

[Gokhale et al., 1990a]
Maya Gokhale, William Holmes, Andrew Kosper, Dick Kunze, Dan Lopresti, Sara Lucas, Ronald Minnich, and Peter Olsen. SPLASH: A reconfigurable linear logic array. In International Conference on Parallel Processing, pages I-526-I-532, 1990.

[Gokhale et al., 1990b]
Maya Gokhale, Andrew Kosper, Sara Lucas, and Ronald Minnich. The logic description generator. In Proceedings of the International Conference on Application Specific Array Processing, pages 111-120, 1990.

[Gokhale et al., 1991]
Maya Gokhale, William Holmes, Andrew Kosper, Sara Lucas, Ronald Minnich, and Douglas Sweely. Building and using a highly parallel programmable logic array. IEEE Computer, pages 81-89, January 1991.

[Greene et al., 1993]
Jonathan Greene, Esmat Hamdy, and Sam Beal. Antifuse field programmable gate array. Proceedings of the IEEE, 81(7):1042-1056, July 1993.

[Guccione, 1994]
Steven A. Guccione. List of FPGA-based computing machines. World Wide Web page http://www.utexas.edu/~ guccione/HW_list.html, 1994.

[Hardenbergh, 1994]
Hal W. Hardenbergh. CPU performance: Where are we headed? Dr. Dobb's Journal, pages 30-38, January 1994.

[Hartenstein et al., 1991]
Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Reidmüller, Karin Schmidt, and Michael Weber. A novel ASIC design approach based on a new machine paradigm. IEEE Journal of Solid-State Circuits, 26(7):975-989, July 1991.

[Hatcher and Quinn, 1991]
Philip J. Hatcher and Michael J. Quinn. Data-Parallel Programming on MIMD Computers. The MIT Press, Cambridge, MA, 1991.

[Hennessy and Patterson, 1990]
John L. Hennessy and David A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, Inc., 1990.

[Hill and Cassiday, 1990]
Dwight D. Hill and Daniel R. Cassiday. Preliminary description of tabula rasa, an electrically reconfigurable hardware engine. In IEEE International Conference on Computer Design, pages 391-394, 1990.

[Hillis and Guy L. Steele, 1986]
W. Daniel Hillis and Jr. Guy L. Steele. Data parallel algorithms. Communications of the ACM, 29(12):1170-1183, December 1986.

[Hillis, 1985]
W. Daniel Hillis. The Connection Machine. The MIT Press, Cambridge, MA, 1985.

[Hwang and Briggs, 1984]
Kai Hwang and Faye A. Briggs. Computer Architecture and Parallel Processing. McGraw-Hill Book Company, 1984.

[Hwang and Xu, 1988]
Kai Hwang and Zhiwei Xu. Multipipeline networking for compound vector processing. IEEE Transactions on Computers, 37(1):33-47, January 1988.

[Kautz et al., 1968]
William H. Kautz, Karl N. Levitt, , and Abraham Waksman. Cellular interconnection arrays. IEEE Transactions on Electronic Computers, C-17(5):443-451, May 1968.

[Kautz, 1970]
William H. Kautz. Cellular logic-in-memory arrays. IEEE Transactions on Computers, C-18:719-727, August 1970.

[Kean and Feng, 1987]
Tom Kean and Genbao Feng. Configurable logic: An approach to rapid implementation of ASIC's. Technical Report CSR-234-87, University of Edinburgh, Department of Computer Science, June 1987.

[Kean and Gray, 1989]
Tom Kean and John Gray. Configurable hardware: Two case studies of micro-grain computation. In J. McCanny and E. Swartzlander Jr., editors, Systolic Array Processors, pages 310-319. Prentice Hall, 1989.

[Kean, 1989]
Thomas Andrew Kean. Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation. PhD thesis, University of Edinburgh, Department of Computer Science, January 1989.

[Kernighan and Ritchie, 1988]
Brian W. Kernighan and Dennis M. Ritchie. The C Programming Language. Prentice Hall Publishing Company, second edition edition, 1988.

[Kogge and Stone, 1973]
Peter M. Kogge and Harold S. Stone. A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Transactions on Computers, C-22(8):786-793, August 1973.

[Kogge, 1974]
Peter M. Kogge. Parallel solution of recurrence problems. IBM Journal of Research and Development, 18(2):138-148, March 1974.

[Kogge, 1981]
Peter M. Kogge. The Architecture of Pipelined Computers. McGraw-Hill, 1981.

[Koren and Silberman, 1983]
Israel Koren and Gabriel M. Silberman. A direct mapping of algorithms onto VLSI processing arrays based on the data flow approach. In Proceedings of the International Conference on Parallel Processing, pages 335-337, 1983.

[Koren et al., 1988]
Isreal Koren, Bilha Mendelson, Irit Peled, and Gabriel M. Silberman. A data-driven VLSI array for arbitrary algorithms. IEEE Computer, pages 30-43, October 1988.

[Kruskal et al., 1985]
Clyde P. Kruskal, Larry Rudolph, and Marc Snir. The power of parallel prefix. IEEE Transactions on Computers, C-34(10):965-968, October 1985.

[Kung, 1982]
H. T. Kung. Why systolic architectures? IEEE Computer, 15(1):37-46, January 1982.

[Kung, 1984]
Sun-Yuan Kung. On computing with systolic/wavefront array processors. Proceedings of the IEEE, 72(7):867-884, July 1984.

[Ladner and Fischer, 1980]
Richard E. Ladner and Michael J. Fischer. Parallel prefix computation. Journal of the ACM, 27(4):831-838, October 1980.

[Lipovski and Tripathi, 1977]
G. Jack Lipovski and Anand Tripathi. A reconfigurable varistructure array processor. In Proceedings of the 1977 International Conference on Parallel Processing, pages 165-174. IEEE Press, 1977.

[Lippmann, 1987]
Richard P. Lippmann. Introduction to computing with neural nets. IEEE Acoustics, Speech and Signal Processing, pages 4-22, April 1987.

[Lipton and Lopresti, 1985]
Richard Lipton and Daniel Lopresti. A systolic array for rapid string comparison. In Henry Fuchs, editor, 1985 Chapel Hill Conference on Very Large Scale Integration, pages 363-376. Computer Science Press, 1985.

[Lipton and Lopresti, 1986]
Richard Lipton and Daniel Lopresti. Comparing long strings on a short systolic array. In Will Moore, Andrew McCabe, and Roddy Urquhart, editors, Systolic Arrays, pages 181-190. Adam Hilger, 1986.

[Logue et al., 1975]
J. C. Logue, N. F. Brickman, F. Howley, J. W. Jones, and W. W. Wu. Hardware implementation of a small system in programmable logic arrays. IBM Journal of Research and Development, pages 110-119, March 1975.

[Lopresti, 1987]
Daniel P. Lopresti. P-NAC: A systolic array for comparing nucleic acid sequences. IEEE Computer, pages 98-99, July 1987.

[Ma and Taylor, 1990]
Gin-Kou Ma and Fred J. Taylor. Multiplier policies for digital signal processing. IEEE ASSP Magazine, 7(1):6-20, January 1990.

[Mano, 1979]
M. Morris Mano. Digital Logic and Computer Design. Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1979.

[McCulloch and Pitts, 1943]
Warren McCulloch and Walter Pitts. A logical calculus of the idea immanent in nervous activity. Bulletin of Mathematical Biophysics, 5:115-153, 1943.

[McMahon, 1986]
Frank H. McMahon. The livermore fortran kernels: A computer test of the numerical performance range. Technical Report UCRL-53745, Lawrence Livermore National Laboratory, December 1986.

[Mead and Conway, 1980]
Carver Mead and Lynn Conway. Introduction to VLSI Systems. Addison Wesley Publishing, 1980.

[Minnick, 1964]
Robert C. Minnick. Cutpoint cellular logic. IEEE Transactions on Electronic Computers, EC-13(6):685-698, December 1964.

[Minnick, 1967]
Robert C. Minnick. A survey of microcellular research. Journal of the ACM, 14(2):203-241, 1967.

[Moore and Luk, 1991]
Will Moore and Wayne Luk, editors. FPGAs. Abingdon EE&CS Books, Abingdon, England, 1991. edited from the 1991 International Workshop on Field Programmable Logic and Applications.

[Moore and Luk, 1993]
Will Moore and Wayne Luk, editors. More FPGAs. Abingdon EE&CS Books, Abingdon, England, 1993. edited from the 1993 International Workshop on Field Programmable Logic and Applications.

[Padua and Wolf, 1986]
David A. Padua and Michael J. Wolf. Advanced compiler optimizations for supercomputers. Communications of the ACM, 29(12):1184-1201, December 1986.

[Patil and Welch, 1979]
Suhas S. Patil and Terry A. Welch. A programmable logic approach for VLSI. IEEE Transactions on Computers, c-28(9), September 1979.

[Pfeiffer et al., 1990]
Wayne Pfeiffer, Arnold Alagar, Anke Kamrath, Robert H. Leary, and Jack Rogers. Benchmarking and optimization of scientific codes on the CRAY X-MP, CRAY-2 and SCS-40 vector computers. The Journal of Supercomputing, 4(2):131-152, June 1990.

[Rose et al., 1993]
Jonathan Rose, Abbas El Gamal, and Alberto Sangiovanni-Vincentelli. Architecture of field-programmable gate arrays. Proceedings of the IEEE, 81(7):1013-1029, July 1993.

[Sabot, 1988]
Gary W. Sabot. The Paralation Model: Architecture Independent Parallel Processing. MIT Press, Cambridge, Massachusetts, 1988.

[Sangiovanni-Vincentelli et al., 1993]
Alberto Sangiovanni-Vincentelli, Abbas El Gamal, and Jonathan Rose. Synthesis methods for field programmable gate arrays. Proceedings of the IEEE, 81(7):1057-1083, July 1993.

[Shand et al., 1991]
M. Shand, P. Bertin, and J. Vuillemin. Hardware speedups in long integer multiplication. Computer Architecture News, 19(1):106-113, March 1991.

[Shand, 1992]
Mark Shand. Measuring system performance with reprogrammable hardware. Technical Report 19, DEC Paris Research Laboratory, 1992.

[Shoup, 1970]
Richard G. Shoup. Programmable Cellular Logic Arrays. PhD thesis, Carnegie-Mellon University, Computer Science Department, March 1970.

[Snyder, 1982]
Lawerence Snyder. Introduction to the configurable, highly parallel computer. IEEE Computer, 15(1):47-56, January 1982.

[Stone, 1990]
Harold S. Stone. High-Performance Computer Architecture. Addison-Wesley Publishing Company, 1990.

[Sutherland and Mead, 1977]
Ivan E. Sutherland and Carver A. Mead. Microelectronics and computer science. Scientific American, 253(9):210-228, September 1977.

[Sutherland, 1989]
Ivan E. Sutherland. Micropipelines. Communications of the ACM, 32(6):720-738, June 1989. 1989 ACM Turing Award Lecture.

[Swartzlander, 1990]
Earl E. Swartzlander, Jr., editor. Computer Arithmetic, volume 1. IEEE Computer Society Press, Los Alamitos, California, 1990.

[Tanaka et al., 1989]
Toshiaki Tanaka, Tsutomu Kobayashi, and Osamu Karatsu. HARP: Fortran to silicon. IEEE Transactions on Computer-Aided Design, 8(6):649-660, June 1989.

[Tanaka et al., 1990]
Yoshikazu Tanaka, Kyouko Iwasawa, Yukio Umetani, and Shizuo Gotou. Compiling techniques for first-order linear recurrences on a vector computer. The Journal of Supercomputing, 4(1):63-82, March 1990.

[Toffoli and Margolus, 1987]
Tommaso Toffoli and Norman Margolus, editors. Cellular Automata Machines. The MIT Press, Cambridge, Massachusetts, 1987.

[Trimberger, 1993]
Stephen Trimberger. A reprogrammable gate array and applications. Proceedings of the IEEE, 81(7):1030-1041, July 1993.

[Ullman, 1984]
Jeffrey D. Ullman. Computational Aspects of VLSI. Computer Science Press, Inc., Rockville, Maryland, 1984.

[Varghese et al., 1993]
Joseph Varghese, Michael Butts, and Jon Batcheller. An efficient logic emulation system. IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, 1(2):171-174, June 1993.

[Viitanen et al., 1990]
Jouko Viitanen, Tapio Korpiharju, and Hannu Kiminkinen. Mapping algorithms onto the TUT cellular array processor. In International Conference on Application Specific Array Processors, pages 235-246, 1990.

[Wahlstrom, 1967]
Sven E. Wahlstrom. Programmable logic arrays -- cheaper by the millions. Electronics, 40(25):90-95, December 11 1967.

[Wolfe and Shen, 1988]
Andrew Wolfe and John P. Shen. Flexible processors: A promising application-specific processor design approach. In Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture, pages 30-39. IEEE Press, 1988.

[Xil, 1991]
Xilinx, Inc. The Programmable Gate Array Data Book, 1991.

[Zorpette, 1992]
Glenn Zorpette. The power of parallelism. IEEE Spectrum, 29(9):28-33, September 1992.