High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, Proc. SPIE 2914, John Schewel, Editor.

From papers presented at the International Society for Optical Engineering (SPIE) Photonics East conference held in Boston, Massachusetts on November 20--21, 1996.

Steven Guccione / guccione@NOSPAM.io.com

[Andraka, 1996]

R. Andraka. Dynamic hardware video processing platform. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 90-99, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Babb et al., 1996]

J. W. Babb, M. I. Frank, and A. Agarwal. Solving graph problems with dynamic computation structures. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 225-236, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Beechick et al., 1996]

A. Beechick, S. Casselman, and L. D. Yarbrough. Internal sorting and FPGA. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 66-71, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Bittner, Jr. et al., 1996]

R. A. Bittner, Jr., P. M. Athanas, and M. D. Musgrove. Colt: an experiment in wormhole runtime reconfiguration. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 187-195, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Brown, 1996]

G. Brown. User-configurable data acquisition systems. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 54-64, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Casselman, 1996]

S. Casselman. Reconfigurable-logic-based fiber channel network card. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 180-186, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Chandran, 1996]

H. Chandran. Configurable adaptive signal processing subsystem for various applications in telemetry and navigation and and telecommunication. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 84-89, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Chow and Alnuweiri, 1996]

H. A. Chow and H. M. Alnuweiri. FPGA-based transformable coprocessor for MPEG video processing. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 308-320, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Covert, 1996]

P. J. Covert. Design tips and experiences in using reconfigurable FLEX logic. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 124-132, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[DeMarco et al., 1996]

J. J. DeMarco, J. B. Smathers, T. D. Solberg, and S. Casselman. Application of FPGA technology to performance limitations in radiation therapy. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 295-299, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Dick and Harris, 1996]

C. H. Dick and F. J. Harris. Polynomial-transform-based approach to computing 2D DFTs using reconfigurable computers. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 72-83, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Elnaggar et al., 1996]

A. Elnaggar, H. M. Alnuweiri, and M. R. Ito. Embedding large multidimensional DSP computations in reconfigurable logic. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 300-307, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Erdogan and Wahab, 1996]

S. S. Erdogan and A. B. Wahab. Hierarchical decomposition model for reconfigurable architecture. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 141-151, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Fawcett and Watson, 1996]

B. K. Fawcett and J. Watson. FPGA applications in digital video systems. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 283-294, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Ferguson, 1996]

L. Ferguson. Image processing using reconfigurable FPGAs. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 110-121, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Fross et al., 1996]

B. K. Fross, R. L. Donaldson, and D. J. Palmer. PCI-based WILDFIRE reconfigurable computing engines. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 170-179, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Gokhale et al., 1996]

M. Gokhale, J. Kaba, A. Marks, and J. Kim. Malleable architecture generator for FPGA computing. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 208-217, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Goslin, 1996]

G. R. Goslin. Guide to using field programmable gate arrays (FPGAs) for application-specific digital signal processing performance. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 321-331, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Gulak and D'Mello, 1996]

C. Gulak and D. R. D'Mello. Review of field-programmable analog arrays. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 152-169, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Hartenstein et al., 1996]

R. W. Hartenstein, J. Becker, M. Herr, and U. Nageldinger. Codesign and highperformance computing: scenes and crisis. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 271-282, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Herzen, 1996]

B. Von Herzen. 250-MHz correlation using high-performance reconfigurable computing engines. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 34-43, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Leeser et al., 1996]

M. F. Leeser, S. Tarafdar, and Y. Li. Rapid prototyping of datapath intensive architectures with HML: an abstract hardware description language. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 259-270, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Margolus, 1996]

N. Margolus. Large-scale logic array computation. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 341-352, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Paar et al., 1996]

K. J. Paar, P. M. Athanas, and C. M. Edwards. Implementation of a finite difference method on a custom computing platform. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 44-53, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Peterson and Athanas, 1996]

J. B. Peterson and P. M. Athanas. Resource pools: an abstraction for configurable computing codesign. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 218-224, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Reeves et al., 1996]

K. Reeves, K. Sienski, and C. Field. Reconfigurable hardware accelerator for embedded DSP. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 332-340, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Savaria et al., 1996]

Y. Savaria, G. Bois, P. Popovic, and A. Wayne. Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 195-205, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Schewel, 1996]

John Schewel, editor. High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914. SPIE -- The International Society for Optical Engineering, Bellingham, WA, November 1996. Proceedings from the session at the SPIE Photonics East conference held in Boston, Massachusetts on November 20-21, 1996.

[Smith, 1996]

S. J. Smith. Programmable hardware for reconfigurable computing systems. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 133-140, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Tangtrakul et al., 1996]

A. Tangtrakul, B. Yeung, and T. A. Cook. Signed-digit online floating-point arithmetic for FPGAs. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 2-13, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Taylor, 1996]

B. Taylor. DSP filters in FPGAs for image processing applications. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 100-109, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Tenca and Ercegovac, 1996]

A. F. Tenca and M. D. Ercegovac. Design of high-radix digit slices for online computations. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 14-25, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Weaver et al., 1996]

C. F. Weaver, C. C. Weems, and K. S. McKinley. Compiling high-level languages for configurable computers: applying lessons from heterogeneous processing. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 249-258, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Yu and Xing, 1996]

W. W. H. Yu and S. Xing. Performance evaluation of FPGA implementations of high-speed addition algorithms. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 26-33, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.

[Zhong and Martonosi, 1996]

P. Zhong and M. Martonosi. Using recontigurable hardware to customize memory hierarchies. In John Schewel, editor, High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, Proc. SPIE 2914, pages 237-248, Bellingham, WA, October 1996. SPIE -- The International Society for Optical Engineering.