List of FPGA-based Computing Machines

FPGA Devices:

7 Xilinx 3090

On-board RAM:

5Mb 35ns static RAM

External bus:

VME (Sun 3/110 as host)

Interconnect:

Fixed busses

Contact:

Mario Wolczko
now at : Sun Microsystems Labs
Mario.Wolczko@nospam.sun.com
or
Ifor Williams
now at: ADC, 100140.2651@nospam.CompuServe.COM
Project was based at the University of Manchester,
England, 1987-92.

Notes:

See: `Using FPGAs to Prototype New Computer Architectures,' Ifor Williams, in `FPGAs', Abingdon EE&CS Books, edited by Will R Moore and Wayne Luk, 1991, pp 373-382. Mushroom was a prototypical implementation of a RISC architecture designed to support dynamic object-oriented languages.

FPGA Devices:

1 Intel NFX780 in 84-pin PLCC

On-board RAM:

None

External bus:

IBM-PC printer port

Interconnect:

None

Contact:

XESS Corp.
1-800-549-XESS
devb@nospam.vnet.net

Notes:

The nfXboard is a small 4''x 2'' board containing an Intel NFX780 FPGA in 84-pin PLCC package. The nfXboard is programmed using the PLDasm HDL and Intel's free PLDshell Plus programming environment. Configuration files are downloaded to the nfXboard through the PC printer port using the JTAG protocol. Additional signals from the printer port can be used to exercise the downloaded design and the results can be observed using the 7-segment LED on the nfXboard. The nfXboard can be used stand-alone or it can be mounted in a protoboard (all 84 pins are made available on two rows of 42 pins each). Since configuration is done using a JTAG stream, it is easy to cascade multiple nfXboards to experiment with larger designs. Inter-FPGA wiring has to be added manually, however. A book accompanies the nfXboard:
"FPGA Workout: Beginning Exercises with the Intel FLEXlogic FPGA". Softcover, 240 pp., 120 illustrations, and index. ISBN 0-9642187-0-4.
This book shows how to use FPGAs to build digital systems ranging from simple combinational logic up to a 4-bit microcontroller. All PLDasm examples in the book can be downloaded into the nfXboard and tested.
The nfxboard has been replaced by newer hardware. See the XESS web site for further information.

FPGA Devices:

2 Xilinx 3090

On-board RAM:

64K SRAM / 1M DRAM

External bus:

ISA

Interconnect:

Fixed

Contact:

National Technology, Inc.
9500 South 500 West Suite #104
Sandy, UT 84070
Phone: (801) 561-0114
FAX: (801) 561-4702
Email: bruceg@nospam.metalith.com

Notes:

The nP the Nano Processor (nP) is an early commercially available board from NTI.

FPGA Devices:

4 XC4010E

On-board RAM:

Two 64k x 16-bitsSRAM banks
4 angled 72-pin SIMM DRAM connectors

External bus:

PCI

Interconnect:

2x2 matrix of PQ208 footprints

Contact:

Mark Shand
shand@nospam.pa.dec.com

Notes:

See: http://www.research.digital.com/SRC/pamette

FPGA Devices:

25 Xilinx 3020

On-board RAM:

0.5 MB

External bus:

VME

Interconnect:

Fixed mesh

Contact:

Patrice Bertin
Paris Research Laboratory
Digital Equipment Corporation
85, avenue Victor Hugo
92500 Rueil-Malmaison, France
bertin@nospam.prl.dec.com or
Partice.Bertin@nospam.inria.fr

Notes:

The first board from the Programmable Active Memories (PAM) project at DEC PRL. Replaced by the DEC PAM perle-1.

FPGA Devices:

24 Xilinx 3090

On-board RAM:

4MB SRAM

External bus:

DEC TURBOchannel

Interconnect:

Fixed mesh

Contact:

Patrice Bertin
Paris Research Laboratory
Digital Equipment Corporation
85, avenue Victor Hugo
92500 Rueil-Malmaison, France
bertin@nospam.prl.dec.com or
Partice.Bertin@nospam.inria.fr

Notes:

The second board from the Programmable Active Memories (PAM) project at DEC PRL. Set the record for RSA encryption in 1990. More information is available at http://pam.inria.fr/.

FPGA Devices:

4 Xilinx 3090

On-board RAM:

None

External bus:

16 bit

Interconnect:

None

Contact:

Mike Wazlowski or Harvey Silverman
Laboratory for Engineering Man/Machine Systems
Brown University
Providence, RI 02912
{mew,hfs}@nospam.lems.brown.edu

Notes:

The Processor Reconfiguration through Instruction Set Metamorphosis (PRISM) is notable for its use of C as the description language for the programmable logic.

FPGA Devices:

3 Xilinx 4010 per processing node

On-board RAM:

128K x 32 per 4010

External bus:

64 bit writes, 32 bit reads, on processor bus (it's not external)

Interconnect:

Inverted tree, or none, application selectable

Contact:

Mike Wazlowski or Harvey Silverman
Laboratory for Engineering Man/Machine Systems
Brown University
Providence, RI 02912
{mew,hfs}@nospam.lems.brown.edu

Notes:

Each Processor Reconfiguration through Instruction Set Metamorphosis (PRISM-II) board is a node in the Armstrong III loosely-coupled parallel processor. The host CPU is a 33Mhz AMD Am29050 RISC processor. There are 20 nodes that are connected by a reconfigurable (of course) interconnection topology.

FPGA Devices:

12 PROTEUS (Custom designed SRAM-base FPGA)

On-board RAM:

4 dual-port RAMs (8K x 16bit x 4)

External bus:

Original bus

Interconnect:

2 opposing groups of PROTEUS chips (6 PROTEUS for each direction)

Contact:

Kazuhiro Hayashi
NTT Optical Network Systems Laboratories
1-2356 Take Yokosuka-shi
Kanagawa 238-03 JAPAN
Email: kazu@nospam.exa.onlab.ntt.jp

Notes:

Line interface modules for ProBoard: 156Mbps X 4 Optical interface, 6.3Mbps X 2 coaxial cable interface with clock recovery circuit using time stamp method, 1.5Mbps X 2 metalic cable interface with clock recovery circuit using time stamp method, and HIPPI interface.

FPGA Devices:

52 - Xilinx XC-4010E-4 FPGA OR Xilinx XC-4013E-3 FPGA -- P4 Series

40 - Xilinx XC-4010E-4 FPGA OR Xilinx XC-4013E-3 FPGA -- P3 Series

26 - Xilinx XC-4010E-4 FPGA OR Xilinx XC-4013E-3 FPGA -- P2 Series

14 - Xilinx XC-4010E-4 FPGA OR Xilinx XC-4013E-3 FPGA -- P1 Series

On-board RAM:

8 MB SRAM 256K dual-ported SRAM -- P4 Series

6 MB SRAM 256K dual-ported SRAM -- P3 Series

4 MB SRAM 256K dual-ported SRAM -- P2 Series

2 MB SRAM 256K dual-ported SRAM -- P1 Series

Interconnect:

24 - ICUBE Programmable Interconnect Devices -- P4 Series

18 - ICUBE Programmable Interconnect Devices -- P3 Series

14 - ICUBE Programmable Interconnect Devices -- P2 Series

12 - ICUBE Programmable Interconnect Devices -- P1 Series

External bus:

Bus Independant

Currently --- Single Slot SBus Plugin Interface Board for SUN Workstation Compatible Computers

Contact:

John Schewel

Virtual Computer Corporation

6925 Canby Ave #103

Reseda CA 91335 USA

Email: jas@nospam.vcc.com

Tel: (818) 342-8294 Fax: (818) 342-0240
Visit Our Web Site at: VCC's Home Page

Notes:

The P Series Virtual Computer^tm (P4), is a single board desktop reconfigurable computer. The P Series, with massive reconfigurable logic (over 650,000 logic gates), delivers supercomputer performance and speed at a fraction of the cost of a supercomputer. The P-Series Virtual Computer plugs into existing computer systems via an interface card. (SBus Compatable Workstation currently available.)
More information on the P Series Virtual Computer is available at: VCC's Website for the P Series Virtual Computer.

FPGA Devices:

1 Xilinx XC4005 or larger XC4000 series device

On-board RAM:

64K Words (16 bit words)

External bus:

R16 bus, 16 bit addr, 16 bit data, Synchronous at 20 MHz

Interconnect:

Any

Contact:

Philip Freidin
Fliptronics
468 S. Frances St,
Sunnyvale, CA 94086
Phone: (408) 737-8060
email: fliptron@nospam.netcom.com

Notes:

A 16 bit RISC processor that requires 75% of an XC4005, 16 general registers, 4 stage pipeline, Target speed is 20 MHz. Can be integrated with peripherals on 1 FPGA, and ISET can be extended. Instruction set is similar to AMD 29000 RISC, and includes 3 address instructions like ADD R4,R7,R12 as well as two and one address instructions. Memory interface is a pipelined load/store operation. I/O space can be upto 64K of 16bit I/O locations. Software currently includes a macro assembler, gate level simulator, ANSI C compiler (but no linker yet), and a debug monitor.

FPGA Devices:

3 Xilinx 4010

On-board RAM:

320K SRAM

External bus:

ISA

Interconnect:

2 Aptix FPICs

Contact:

Herman Schmit
ECE Department
Carnegie Mellon University
Pittsburgh, PA 15213
Phone: (412) 268-2476

Notes:

Integrated with a behavioral synthesis tool which allows specification of the desired algorithm in behavioral Verilog or C.

FPGA Devices:

Xilinx XC4010E

On-board RAM:

256KB, 1MB SRAM. Industry Pack Modules.

External bus:

ISA

Input / Output:

Single slot Industry Pack carrier.

Contact:

Embedded Solutions Ltd.
83 Gipsy Lane
Wokingham
Berks
RG40 2BW, UK
E-mail sales@nospam.embedded-solutions.ltd.uk

Notes:

The RC1000-II is a supported target platform for the Handel-C V2.0 programming language. Unlike other programming languages, the output of this compiler is not a binary file; it is a net list. The Handel-C tools enable a software engineer to target directly FPGAs in a similar fashion to classical microprocessor cross-compiler development tools, without recourse to a Hardware Description Language. Thereby allowing the software engineer to realise directly the raw real-time processing capability of the FPGA. With Handel-C complete systems can be designed as a programming task, using only conventional and easily available programming skills. Source code and schematics are commercially available for the RC1000-II to enable OEMs to rapidly produce custom variations of the design. More information is available at: http://www.embedded-solutions.ltd.uk

FPGA Devices:

Xilinx XC4085XL or XC40125XV and future package compatible devices.

On-board RAM:

8MB of SRAM

External bus:

PCI

Interconnect:

2 x PMC daughter-board sites and a 50 pin unassigned header

Contact:

Embedded Solutions Ltd. 83 Gipsy Lane
Wokingham
Berks
RG40 2BW, UK
E-mail: sales@nospam.embedded-solutions.ltd.uk

Notes:

The RC1000-PP hardware platform is a standard PCI bus card. The 8Mb of SRAM are directly connected to the FPGA in four 32 bit wide memory banks. The memory is also visible to the host CPU across the PCI bus as if it were normal memory. Each of the 4 banks may be granted to either the host CPU or the FPGA at any one time. Data can therefore be shared between the FPGA and host CPU by placing it in the SRAM on the board. It is then accessible to the FPGA directly and to the host CPU either by DMA transfers across the PCI bus or simply as a virtual address.

The board is equipped with two industry standard PMC connectors for directly connecting other processors and I/O devices to the FPGA; a PCI-PCI bridge chip also connects these interfaces to the host PCI bus, thereby protecting the available bandwidth from the PMC to the FPGA from host PCI bus traffic. The 50 pin unassigned header is provided for either inter-board communication, allowing multiple RC1000-PPs to be connected in parallel or for connecting custom interfaces.

The support software provides Windows®95 and NT®4.0+ drivers for the board, together with application examples written in Handel-C, or the board may be programmed using the Xilinx XACTstep™ tools and other EDA tools. More information is available at: http://www.embedded-solutions.ltd.uk

FPGA Devices:

16 x (one 3064, four 3042, two 3020/3030, all Xilinx)

On-board RAM:

None accessible from the FPGAs
16 MByte DRAM, 2 MByte SRAM on each processor bus
4 32-bit wide FIFO-channels between processor and FPGAs

External bus:

VME, special designed communication streams controlled by FPGAs

Interconnect:

Some fixed buses

Contact:

Jon G. Solheim
Department of Computer Systems and Telematics
Norwegian Institute of Technology
N-7034 Trondheim
email: jon@nospam.idt.unit.no

Notes:

RENSS is a special purpose computer for Neural Networks. It has 16 TMS320C30-33 as processing elements, and a dynamic reconfigurable communication system. The FPGAs are accessible from the processor, and thereby usable for implementing co-processor routines in hardware, as well as intelligent communication (mixing communication and computation). All FPGAs are configured the processor.

FPGA Device:

1 Xilinx XC6216

On-board RAM:

None

External bus:

PS2 (bidirectionnal) parallel port

Interconnect:

multi I/O (with a miniature 50 pins connector)

Contact:

Jean Conter
ENSEEIHT Informatique-équipe VPCAB
2 rue Camichel
31071-TOULOUSE-FRANCE
Email: conter@nospam.enseeiht.fr

Notes:

RHO: Reconfigurable Hardware Overdrive
It is probably the smallest implementation of the XC6216 RPU : one GAL (16V8), one oscillator (DS1075), two latches and a XC6216HT144 have been placed on a dongle sized board (45*45 mm).
This 'coprocessing dongle' connects directly to a regular parallel port. An interactive development system based on the MDL language is under completion.
The direct I/O access provides a simple solution for developping logic analyzers, pulse pattern generators and general purpose interfaces (image processing, cryptography,...)

FPGA Devices:

8 Altera FLEX 81188

On-board RAM:

2 MB SRAM

External bus:

ISA

Interconnect:

Fixed buses / programmable interconnect (see Description)

Contact:

Nick Tredennick
Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
Phone: (408) 894-7000
Email: nickt@nospam.altera.com

Notes:

The Reconfigurable Interconnect Peripheral Processor (RIPP) contains up to 8 Altera FLEX 81188 parts, each of which may be replaced by an ICUBE IQ160 Field Programmable Interconnect Device (FPID). Devices are grouped into 4 pairs of 2 devices, each sharing an SRAM device. Designed by David E. Van den Bout of the Anyboard project.

FPGA Devices:

8 Altera FLEX EPF81188

On-board RAM:

2 MB SRAM

External bus:

ISA

Interconnect:

Fixed buses

Contact:

Stephen Smith
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Tel: (408) 544-7666
E-mail: sjsmith@nospam.altera.com
WWW Page: http://www.altera.com/html/programs/phd.html

Notes:

The Reconfigurable Interconnect Peripheral Processor (RIPP10) contains up to 8 Altera FLEX 81188 parts and four SRAM devices. Devices are grouped into 4 pairs of 2 devices, each sharing an SRAM device. Designed by David E. Van den Bout of the Anyboard project. These platforms are available for free to qualified researchers.

FPGA Devices:

7 Xilinx XC4013/board, total of 9 boards

On-board RAM:

2 MB SRAM controlled by 2 XC4013s (first level memory/cache)
8 MB SRAM controlled by 3 XC4013s (second level memory/cache)
96 MB DRAM controlled by 2 XC4013s (third level memory)

External bus:

SCSI connection to a Sun SPARC host, custom on-board bus and backplane FutureBus+.

Interconnect:

??

Contact:

Michel Dubois
Dept. of Electrical Engineering - Systems
University of Southern California
Los Angeles, CA 90089-2562
Email: dubois@nospam.paris.usc.edu

Notes:

The USC Rapid Prototyping engine for Multiprocessors (RPM) is used for multiprocessor experimentation. A preprint of a report to appear on IEEE Computer Magazine in February 1995 obtained through ftp.
A homepage for the USC RPM is also available.

FPGA Devices:

1 Xilinx 3064 or optional 3042

On-board RAM:

128KW(24-bit) (shared with DSP56002)

External bus:

SBus & Flexible

Interconnect:

See notes below.

Contact:

Michael C. Peck
President
Berkeley Camera Engineering
1122 B Street, Suite 219
Hayward, CA 94541-4227
Phone: 510-889-6960
Fax: 510-889-7606
email: mikep@nospam.bce.com

Notes:

The S56X2 is an SBus card that contains a 66MHz Motorola 56002 DSP, a Xilinx 3064 memory 128K words (24-bits) SRAM. The 3064 sits directly on the 56002 memory bus and has a DC37F connector to the outside world for user defined I/O. New to the S56X2 version is RS-422 I/O (4 pair out, 4 pair in) between some of the Xilinx and the DC37F pack panel connector. The Xilinx can be accessed from the 56002 with two signals mapped from the SBus through the PAL.

Replaces DSP-56X.

FPGA Devices:

Choice between any Xilinx 208 pin part or Altera 240 pin part. Up to four in any combination.

On-board RAM:

0.5 MB of SRAM

External Bus:

PCI or SBus

Interconnect:

Local bus and up to 87 additional lines.

Contact:

stuart.adams@nospam.east.sun.com

Notes:

Current Xilinx boards have been populated with XC4013E. Bare boards are available for other devices. More information available at: SBX+

FPGA Devices:

Portable VHDL design allows operation on Lucent, Altera or Xilinx. Requires less than 20% of gates on larger FPGA devices. Evaluation board uses 80% of gates on a Lucent OR2CA15 device (including RAM and ROM).

On-board RAM:

512 x 12 instruction ROM, 32 bytes RAM. RAM and ROM can be scaled up or down to fit budget and application.

External bus:

Microcontroller type parallel ports.

Interconnect:

Typical Microcontroller I/O via three 8-bit I/O ports. Device is intended to form a custom microcontroller on a single FPGA.

Contact:

Wade Peterson, Silicore Corporation
3525 East 27th Street, No. 301
Minneapolis, MN 55406
e-mail: peter299@maroon.tc.umn.edu
web page: http://www.silicore.net/

Notes:

8-bit RISC processor delivered as synthesizable VHDL soft core. This device is 100% software compatible with the PIC16C55 ('PIC(tm)' processor) from Microchip Technology. Design can be scaled up or down to match other processors in the same family. Assembler, 'C', Fuzzy Logic and BASIC software tools available. Microcomputer instructions reside in ROM inside of FPGA. A VHDL parallel port interface is included to support application code development through a PC-compatible parallel port interface (software included). Evaluation board available.

FPGA Devices:

3 Xilinx XC4010s

On-board RAM:

2 256Kx32bit SRAMs for user data 1 128Kx8bit SRAM for on-board configuration cache

External bus:

SBus

Interconnect:

Fixed

Contact:

Andreas Koch
Institut f"ur theoretische Informatik
Abteilung Entwurf Integrierter Schaltungen
Gaussstr. 11
D-38106 Braunschweig, Germany
Email: a.koch@nospam.tu-bs.de

Notes:

See FPL'93 Oxford workshop

FPGA Devices:

16 Algotronix CAL1024

On-board RAM:

4 MB DRAM (not directly connected to CAL1024s)

External bus:

Custom / 10 Mbps Transputer serial links

Interconnect:

Fixed grid with expansion to other boards

Contact:

George Milne
Advanced Computing Research Centre
University of South Australia
The Levels, SA 5095
Australia
E-mail: milne@nospam.cis.unisa.edu.au
Telephone: +61 8 8302 3943

Notes:

The Scalable Parallel Architecture for Concurrency Experiments (SPACE) is used for research into reconfigurable computers taking advantage of run-time reconfiguration. Simulation of physical systems modelled as cellular automata, and high speed, adaptive information filtering are two such applications. Design entry is through a Macintosh layout editor, Caledonia. A hardware operating system and shell are used for scriptable configuration and system testing. See our Reconfigurable Computing page. SPACE is no longer being built, and has been replaced by SPACE 2 .

FPGA Devices:

8 Xilinx XC6216/XC6264

On-board RAM:

32 MB, 12 ns SRAM SIMMs

External bus:

64-bit @ 33 MHz PCI (host-board) / 2 x 64-bit @ 50 MHz overhead backplane

Interconnect:

2-D toroidal mesh on each board; fixed network to multiple boards

Contact:

Bernard Gunther
Advanced Computing Research Centre
University of South Australia
The Levels, SA 5095
Australia
E-mail: gunther@nospam.cis.unisa.edu.au
Telephone: +61 8 8302 3986

Notes:

This is the second generation Scalable Parallel Architecture for Concurrency Experiments (SPACE). SPACE 2 is a modular reconfigurable computing platform designed to accelerate stream-oriented applications, in particular. A complete platform comprises (typically) a DEC Alpha motherboard with multiple 64-bit PCI slots, hosting at least two processing boards. A passive overhead backplane, carrying two 64-bit board-to-board links, a 17-bit global bus and global clocks, connects the processing boards to form large systems with effectively multiple access ports to the processing board RAM. Each processing board holds 8 XC6216 FPGAs (and soon, XC6264 devices) for computing, and a XC4025E for PCI interface and central control. The toroidal mesh connecting the computing devices provides four 32-bit east-west paths and two 41-bit north-south paths. With the XC6216 devices a pair of boards contains a total of 64-k cells, or approximately a quarter of a million NAND gates equivalent; this capacity will approach 1 million gates equivalent with the pin-compatible XC6264 devices installed.

From 4 MB to 32 MB of 12 ns SRAM SIMMs is available for use as a fast buffer (minimum 200 MB/s bandwidth), general-purpose storage, or to hold configuration contexts. The host processor can access the RAM at 64-bit width, while the FPGAs are limited to 32-bit accesses. Vector address counters in the control logic enable users to transfer vectors to the FPGAs under programmable control, with the option of interrupting the host upon completion. Programmable clock, pulse train, and pulse generators drive the XC6200 global clocks at up to 66 MHz. To speed up device configuration, a number of complete FPGA edit lists, or configuration data, may be preloaded into the board RAM for later hardware-assisted reconfiguration. The entire context of a single XC6216 FPGA can be saved and swapped with a stored context in under one millisecond.

Under Digital UNIX the SPACE 2 boards appear as regular character device files that can be opened, read/written, and seeked. The on-board RAM and the FPGA configuration spaces are accessible in this way. Hardware designs for the XC6216s may be created in VHDL (Synopsys), schematic (Viewlogic), or at gate level using the Xilinx XACTstep 6000 tools. Alternatively, the Trianus integrated FPGA design system from ETHZ may be used to describe XC6200 circuits in the Lola HDL. SPACE 2 systems (including host, software, and processing boards) are available commercially.

FPGA Devices:

2 XC4010s on Reconfigurable Interface Card (G800-RIC)
32 XC4013s grouped in XMODules ( -- see Notes below)

On-board RAM:

Maximum 128 MB DRAM and 4 MB SRAM ( --See Notes below)

External bus:

VESA (VL) Local bus (PCI in September, VME in December)
30 MB/sec memory mapped, 133 MB/sec bus master burst mode
VESA Media Channel)-25 MHz, 32-bit (100 MB/sec) video bus
50 pad VMC edge fingers connect to variety of peripherals
50-pin external connector supports 32-bit I/O devices

Interconnect:

130-pin Virtual Bus Architecture programmable for 32-bit
pipelines, global busses, isolated busses, rings, meshes
All interconnect via Xilinx 4010's on G800 RIC.
Dataflow specific bandwidths vary from 64-bit global bus
@ 17 MHz to 32-bit pipeline @ 76 Mhz. 5 low skew, high
quality clocks are provided per FPGA.

Contact:

bovarga@nospam.gigaops.com
2374 Eunice St.
Berkeley, CA. 94708
Phone (510) 528-8438
Fax (510) 526-6688

Notes:

XMODs have 2 XC4000 series FPGAs on a 2.4" x 3.65" card
with 2 100-pin stacking connectors on the top and bottom.
Up to 8 XMODs may be in 1 stack. Up to 16 XMODs or I/OMODs
of all types on Giga Ops' G-800 RIC in 4 stacks of 4 each.

X210MOD = 2 x XC4010s, 8 MB DRAM, 256 K SRAM
X213MOD = 2 x XC4013s, 8 MB DRAM, 256 K SRAM
VIDMOD = I/O for Composite, S-Video, PAL, SECAM, R,G,B

16 x X213MODs = 32 XC4013s, 128 MB DRAM, 4 MB SRAM
16 x X210MODs = 32 XC4013s, 128 MB DRAM, 4 MB SRAM
XLINK-OS automates the interface between routed Xilinx
configurations and FPGAs. Features include condensing
bit files to single executables, loading files to correct
correct FPGAs in system, assigning addresses to variables
and handling parameter passing.

The Spectrum architecture is open and supported by third
party developers. Contact docmgr@nospam.gigaops.com for Spectrum
specifications. XMODs may be connected to custom boards or
embedded in peripheral devices.

The XC Compiler is a C syntax HDL for Xilinx FPGAs.
The IC Compiler is an ANSI C Compiler for Xilinx FPGAs.
Both compilers are available to qualified researchers.
Video computing, DSP, and I/O libraries are available.

Spectrum2

FPGA Devices on PCI hostbus board (August, 1996):

2 XC4000E(X) series on Reconfigurable Interface Card (G900RIC). The G900 PCI-RIC implements the Xilinx Logicore™PCI Target and Initiator Modes in Xilinx X4013E or other PQ240 FPGAs. A second PQ240 FPGA is used to execute the robust clocking scheme and for data routing and switching and processing.

FPGA Devices for Data Processing/Routing/Switching:

32 XC4000E(X)s series in groups of two on 16 XMODs. Maximum of 640,000 Xilinx gates when XC4020s are used (August, 1996).

On-board Memories:

Maximum 128MB DRAM and 4MB SRAM in 16 XMODs. 512KB surface mounted FLASH, 128KB socketed FLASH, 128KB SRAM on G900

External busses:

Eight 32-bit busses - maximum 128-bit sustained I/O @33MHz - 80MHz. Four 34-bit I/O ports via 68-pin edge fingers. Four 36-bit I/O ports via 50-pin male IDC connectors.

Interconnect:

130-pin Virtual Bus Architecture™ programmable for 32-bit pipelines, global busses, isolated busses, rings, meshes All interconnect is via Xilinx FPGAs on G900 PCI-RIC and is programmable.
Dataflow specific bandwidths vary from 96-bit global busses @ 20 MHz to 32-bit pipelines @ 76 MHz.

Clocks:

8 low skew, high quality clocks per XMOD, 5 per FPGA. These can be internal, external, self-clocking data streams, PLLS, FGENs, XTALs, etc.

Contact:

bo@nospam.gigaops.com
2510 MLK Way
Berkeley, CA. 94708
Phone (510) 848-5446
Fax (510) 848-5667
WWW: http://www.reconfig.com, click on Sponsors, then on Giga Ops logo.

Notes:

XMODs™ hold 2 Xilinx PQ208 FPGAs on a 2.4" x 3.65" card with 2 100-pin stacking connectors on the top and bottom. Up to 8 XMODs may be in 1 stack. Up to 16 XMODs or I/OMODs of all types on Giga Ops' G-900 RIC in 4 stacks of 4 each. XMODs may be embedded in custom computing boards and peripherals. XC5210MOD = 2 x XC5210s, 8MB DRAM, 256KB SRAM (all MEMs optional)
X210EMOD = 2 x XC4010Es, 8MB DRAM, 256KB SRAM
X213EMOD = 2 x XC4013Es, 8MB DRAM, 256KB SRAM
X220EMOD = 2 x XC4020Es, 8MB DRAM, 256KB SRAM
X228EXMOD = 2 x XC4028EXs, 8MB DRAM, 256KB SRAM
4A/DMOD = 4, 12-bit, 40MHz input channels
4VIDINMOD = 4 NTSC/PAL input channels
4GIGAMOD = 4 1.0625 Fiber Channel Ports VIDMOD = 1 NTSC/PAL I/O channel

OS Code Generator for Virtual Hardware Architecture™:

The Spectrum2 Virtual Bus™ enables a wide variety of computing architectures to be implemented. XLINK-OS ™ automates communication interfaces between host apps and Spectrum FPGAs, MEMs, interconnect, and I/O and eliminates the need to write custom drivers for each algorithm or application implemented in a Spectrum Reconfigurable Computing Platform. Features including condensing bit files to single executables, loading files to correct FPGAs in system, assigning addresses to variables, and handling parameter passing.
XLINK-OS and monitor, diagnostic, and I/O Libraries are available as RC-NTDEV-SW (August, 1996) in a WindowsNT environment. The Spectrum architecture is modular, scaleable, reprogrammable, open, and embeddable. Contact docmgr@gigaops.com for the XMOD Design Specification and other papers and presentations.
XL is a language in development at Giga Ops to describe FPGAs.
XL is provided free of charge to Spectrum customers, as is XSCRIPT
and the XL Compiler, which generates .XNF files. These tools will be posted as shareware in 1997.

FPGA Devices:

32 Xilinx 3090

On-board RAM:

4 MB SRAM

External bus:

VME

Interconnect:

Linear array

Contact:

Jeffrey M. Arnold
IDA Supercomputing Research Center
17100 Science Drive
Bowie, MD 20715
Phone: (301) 805-7479
FAX: (301) 805-7602
Phone: jma@nospam.super.org

Notes:

Splash has been replaced by Splash 2.

FPGA Devices:

16 Xilinx 4010

On-board RAM:

8 MB

External bus:

Sun SBus

Interconnect:

Linear array plus crossbar

Contact:

Jeffrey M. Arnold
IDA Supercomputing Research Center
17100 Science Drive
Bowie, MD 20715
Phone: (301) 805-7479
FAX: (301) 805-7602
Phone: jma@nospam.super.org

Notes:

Splash 2 is a successor to Splash.

FPGA Devices:

5 Xilinx 4003, 2 Actel A1280

On-board RAM:

128K SRAM plus 2K fast registers

External bus:

VME and Sun SBus

Interconnect:

Fixed

Contact:

Christian Iseli
Logic Systems Laboratory
Swiss Federal Institute of Technology
CH-1015 Lausanne
Switzerland
Email: chris@nospam.lslsun.epfl.ch

Notes:

A reconfigurable VLIW machine.

FPGA Devices:

3 Xilinx 4008 (upgradable to 4010), 2 Xilinx 4005, 1 Actel A1280 and 1 Actel A1225

On-board RAM:

128K SRAM plus 4K fast registers

External bus:

VME

Interconnect:

Fixed

Contact:

Christian Iseli
Logic Systems Laboratory
Swiss Federal Institute of Technology
CH-1015 Lausanne
Switzerland
Email: chris@nospam.lslsun.epfl.ch

Notes:

A reconfigurable VLIW machine. A newer version of Spyder.
See: http://lslwww.epfl.ch/Staff/CI for more information.

FPGA Devices:

8 iFX 780

On-board RAM:

4-8x 8kx24 Fast Sram

External bus:

Proprietary 16 bit NRZ bus designed for extensive cabling

Interconnect:

420Mb/s 13/24 bit input bus, 30Mb/s OC bus between all nodes, 600Mb/s memory

Contact:

Peter Averkamp
Tech. Univ. of Munich
Physics Dept. E20
James-Franck-Str. 1
D-85748 Garching, Germany
Email: petav@nospam.e20.physik.tu-muenchen.de

Notes:

Used in conjunction with GHz ECL logic for on-line data reduction algorithms in subnanosecond Synchrotron Experiments

FPGA Devices:

Up to four XILINX 4xxx/5xxx family 208 pin QFP

On-board RAM:

None

External bus:

ISA

Interconnect:

None

Contact:

aaps@nospam.erols.com

Notes:

The ST_FPGA system is a family of FPGA development modules which can be used stand alone or mounted on a PC ISA BUS carrier board. Each module consists of up to four XILINX 4xxx/5xxx family 208 pin QFP chips. Up to two modules (8 FPGAs) can be mounted to each carrier board to provide a tremendous amount of flexible FPGA power (Up to 160,000 gates). Each ST-FPGA module can be used stand alone, and has power and over 200 IO and monitoring pins. The ST-FPGA SYSTEM comes with download software and sample VHDL and C code and is ideal for ASIC development.
See http://www.erols.com/aaps/ for more information.

FPGA Devices:

Xilinx 4000E in base, user's choice in computation array

On-board RAM:

4-8 MB SSRAM buffers plus address generators

External bus:

PCI

Interconnect:

Toroidal Mesh

Contact:

bunnie@nospam.mit.edu

Notes:

Tao is a high performance platform for implementing reconfigurable hardware designs. The architecture features a high aggregate throughput and a modular processor core consisting of four reconfigurable macrofunction units embedded in a toroidal interconnect matrix. The modular core allows the platform to be upgraded as reconfigurable hardware technology progresses. A high aggregate throughput is achieved by striking a balance of bandwidth among all the datapath elements, from the PCI bus interface to the intelligent buffers called reformatting engines, to the processor core itself. The platform also features an embedded microcontroller for the support of dynamic reconfiguration schemes. Tao was implemented on a double height PCI card using Xilinx XC4013E-3 FPGAs as the base reconfigurable hardware technology.
See http://web.mit.edu/bunnie/www/tao.html for more information.

FPGA Devices:

1 to 4 Xilinx 40XX in PQ-208 package Currently supported configurations: 4010 + 4003H 4 x 4010

On-board RAM:

Daughter board (see notes)

External bus:

DEC TURBOchannel

Interconnect:

Fixed mesh 2 x 2 matrix

Contact:

Mark Shand
Paris Research Laboratory
Digital Equipment Corporation
85, avenue Victor Hugo
92500 Rueil-Malmaison, France
shand@nospam.prl.dec.com or
shand@nospam.acm.org

Notes:

128 user I/O to daughter board. Synchronous RAM daughter board is under development. Pamette is targeted as a generic I/O adapter with local compute capability. This hardware is from the Programmable Active Memories (PAM) project at DEC PRL.

FPGA Devices:

108 custom FPGA devices/board

On-board RAM:

32MB SRAM/board

External bus:

SCSI

Interconnect:

1 to 16 board system, hardwired design independent 27 chip, 39 layer MCM

Contact:

Rick Amerson
Hewlett-Packard
1501 Page Mill Road
Palo Alto, CA 94304
Email: amerson@nospam.hpl.hp.com

Notes:

Approx 64K gates/board. Designed for rapid turnaround of designs to allow investigation of alternative computing ideas. A program protects hardware from bad designs which might damage it. Simulation only, no in-circuit emulation. 100% automatic place and route. System compiles in under ten seconds per chip. See FCCM'95 for details.

FPGA Devices:

4 Xilinx 4010

On-board RAM:

4 32Kx9 SRAMs

External bus:

Custom to SUN workstation

Interconnect:

Entirely programmable using Aptix AX1024 FPIC

Contact:

Jonathan Rose
Dept. of Electrical and Computer Engineering
University of Toronto
10 King's College Road
Toronto, Ontario
Canada M5S 3G4
Email: jayar@nospam.eecg.toronto.edu

Notes:

The Transmogrifier-1 (TM-1) was operational between 1994 and 1996. It was intended more for rapid prototyping of circuits, but could be used for computing. A technical report on the TM-1 is available on-line. The Transmogrifier C compiler was used to produce circuits for the TM-1, and is freely available.

FPGA Devices:

2 to 32 Altera 10K50 (10K100 soon)

On-board RAM:

4 to 64 banks of ram; each 64 bits wide; each bank is .5 - 2 Mbytes of SRAM or 8-32 Mbytes of DRAM

External bus:

Parallel port to SUN workstation plus 64 to 512 pins of general purpose I/O

Interconnect:

Completely programmable one-hop routing through modified partial crossbar; takes advantage of circuit locality to decrease backplane complexity; uses Icube IQ320 programmable crossbar chips

Contact:

Dave Lewis or Jonathan Rose
Dept. of Electrical and Computer Engineering
University of Toronto
10 King's College Road
Toronto, Ontario
Canada M5S 3G4
Email: {lewis|jayar}@nospam.eecg.toronto.edu

Notes:

The Transmogrifier-2 (TM-2) can have between 1 and 16 modules plugged into a backplane. Each module contains 2 FPGAs, 4 banks of RAM, an I/O connector and a slice of the interconnect network. See "The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System" in the FPGA-97 proceedings or visit the TM-2 web site.

A library of stdio-like routines allow a program on the SUN to transparently communicate with a circuit in the TM-2. The Transmogrifier C compiler can be used to produce circuits for the TM-2, and is freely available.

Status as of April 1997: A two module system is working, and a full sized 16 module system (with 10K100s instead of 10K50s) is being constructed. The latter will have a mechanism for high-speed (20ms) re-programming of each board.

FPGA Devices:

1 Xilinx 4013

On-board RAM:

Not applicable

External bus:

40 Pin DIP socket to any 6502 motherboard (ex:AppleII-C)

Interconnect:

Fixed wire wrapped interconnect

Contact:

Eric Ryherd
VAutomation Inc.
71 Spit Brook Rd.
Suite 306
Nashua NH 03060
Email: eric@nospam.VAutomation.com

Notes:

From synthesizable VHDL model available from VAutomation. Pin compatible replacement for the Rockwell 6502 8 bit uP

FPGA Devices:

2 Xilinx XC4010s

On-board RAM:

32K + 256K SRAM

External bus:

PC (ISA)

Interconnect:

Direct

Contact:

Robert Duncan
Eyepoint Engineering
24 Springpoint Road
Castroville, CA 95012
Email: robert.duncan@nospam.xilinx.com

Notes:

Real time Ray Casting in a volumetric dataset, rendering shaded perspective images from an arbitrary view within the dataset. Applications include medical imaging, volume rendering, etc.

FPGA Devices:

Up to 52 Xilinx 4013

On-board RAM:

Up to 8 MB SRAM, 256K dual-ported SRAM

External bus:

Bus Independent - Current SBus interface

Interconnect:

Up to 24 ICUBE FPID

Contact:

Steve Casselman
Virtual Computer Corporation
Reseda, CA 91335
Phone: (818) 342-8294
FAX: (818) 342-0240
Email: sc@nospam.vcc.com

Notes:

The Virtual Computer P-Series consists of P1, P2, P3 and P4. The P1 has 14 4013s the P2 26 4013s the P3 40 4013s and the P4 has 52 4013s.

FPGA Devices:

5 Altera FLEX81500 and 1 Altera MAX7192

On-board RAM:

6 64Kx32 SRAM modules with 20 ns access time. Each module is upgradable to a 256Kx32 SRAM module.

External bus:

PCI (32 bits, 33.3MHz)

Interconnect:

2D torus network with a 2x2 FLEX81500 matrix (processing matrix).

Contact:

Jocelyn Cloutier
Département d'informatique et de Recherche opérationnelle
Université de Montréal
C.P. 6128, Succ. Centre-Ville
Montréal, Canada
H3C 3J7
Email: cloutier@nospam.iro.umontreal.ca

Notes:

For more informations, look at this WWW site. This project is done in collaboration with AT&T Bell Labs.

FPGA Devices:

2 Xilinx 4013s

On-board RAM:

Not applicable

External bus:

40 Pin DIP socket to any Z80 motherboard (ex:TRS-80)

Interconnect:

Fixed wire wrapped interconnect

Contact:

Gregory Recupero
VAutomation Inc.
71 Spit Brook Rd.
Suite 306
Nashua NH 03060
Email: greg@nospam.VAutomation.com

Notes:

From synthesizable VHDL model available from VAutomation. Pin compatible replacement for the Zilog Z80 8 bit uP.

FPGA Devices:

Actel 1020A (1-3 per processor)

On-board RAM:

External bus:

Interconnect:

Mesh connected wormhole routing

Contact:

Erik Brunvand
CS Dept.
University of Utah
Salt Lake City, UT, 84112
Email: elb@nospam.cs.utah.edu
Phone: (801)581-4345
FAX: (801)581-5843

Notes:

MIMD multiprocessor. Used for self-timed circuit experimentation.

FPGA Devices:

12 Xilinx 3195

On-board RAM:

384K SRAM (32K per FPGA)

External bus:

ISA

Interconnect:

Fixed common bus

Contact:

National Technology, Inc.
9500 South 500 West Suite #104
Sandy, UT 84070
Phone: (801) 561-0114
FAX: (801) 561-4702
Email: bruceg@nospam.metalith.com

Notes:

FPGA Devices:

2 Xilinx XC4010E-3

On-board RAM:

2 x 8K x 8 x 36 cache
2 x 8K x 38 pager (TLB)
8K x 36 scratchpad

External bus:

XKL proprietary 2Gbit/sec active backplane bus

Interconnect:

None

Contact:

Product Information
XKL Systems Corp.
8420 154th Avenue NE
Redmond, WA 98052
np-info@nospam.xkl.com

Notes:

This is the CPU for the TOAD-1, a 36-bit computer instruction-set compatible with the Digital Equipment Corporation PDP-10 family of computers (best known as the DECsystem-10 and DECSYSTEM-20, defined by the respective operating systems Tops-10 and Tops-20).
The FPGAs are used for all arithmetic, including floating-point and byte-selection operations. (Note: The PDP-10 architecture is word-oriented, with byte size and position within the 36-bit word defined by a pointer word which also contains the word address.)

XS40 Board

FPGA Devices:

1 XILINX XC4000, XC5200, or Spartan FPGA in an 84-pin PLCC

On-board RAM:

32 KByte

External bus:

IBM-PC printer port, cascade port, 84-pin breadboard bus

Interconnect:

FPGA, microcontroller, and RAM share a common data/address bus

Contact:

XESS Corp.
1-800-549-XESS
1-919-387-0076
fpga-info@nospam.xess.com
http://www.xess.com/FPGA

Notes:

The XS40 Board is a small 5''x 2'' board containing a XILINX XC4000, XC5200, or Spartan FPGA in an 84-pin PLCC package, an 8031 microcontroller, and a 32 KByte RAM. The XS40 Board is programmed using XILINX's M1 programming environment. The 8031 is programmed using MetaLink's 8051 cross-assembler or any other assembler or compiler that outputs a standard .HEX object file. FPGA bitstream files are downloaded to the XS40 through the PC printer port using the serial bitstream format. 8031 object code is also loaded into the 32 KByte RAM through the printer port. The FPGA is treated as a reconfigurable peripheral of the 8031. Additional signals from the printer port can be used to exercise the downloaded design. The results can be observed using the 7-segment LED on the XS40 or sent back for display on the PC. The XS40 can be used stand-alone or it can be mounted in a breadboard (all the pins for the FPGA, microcontroller and RAM are made available on two rows of 42 pins each). Since configuration is done using a serial bitstream, it is easy to cascade multiple XS40 Boards to experiment with multiprocessor and multi-FPGA systems.
The XS40 is one of the prototyping boards used in Prentice Hall's new lab book on digital design, The Practical Xilinx Designer.
This book shows how to use FPGAs to build digital systems ranging from simple combinational logic up to an 8-bit microcontroller. All the examples in the book can be downloaded into the XS40 and tested.
Additional experiments and materials are presented at the XESS web site.

XS95 Board

FPGA Devices:

1 XILINX XC9500 CPLD in an 84-pin PLCC

On-board RAM:

32 KByte

External bus:

IBM-PC printer port, cascade port, 84-pin breadboard bus

Interconnect:

CPLD, microcontroller, and RAM share a common data/address bus

Contact:

XESS Corp.
1-800-549-XESS
1-919-387-0076
fpga-info@nospam.xess.com
http://www.xess.com/FPGA

Notes:

The XS95 Board is a small 5''x 2'' board containing a XILINX XC9500 CPLD in an 84-pin PLCC package, an 8031 microcontroller, and a 32 KByte RAM. The XS95 Board is programmed using XILINX's M1 programming environment. The 8031 is programmed using MetaLink's 8051 cross-assembler or any other assembler or compiler that outputs a standard .HEX object file. CPLD configuration files are downloaded to the XS40 through the PC printer port using the JTAG port. 8031 object code is also loaded into the 32 KByte RAM through the printer port. The CPLD is treated as a reconfigurable peripheral of the 8031. Additional signals from the printer port can be used to exercise the downloaded design. The results can be observed using the 7-segment LED on the XS95 or sent back for display on the PC. The XS95 can be used stand-alone or it can be mounted in a breadboard (all the pins for the CPLD, microcontroller and RAM are made available on two rows of 42 pins each). Since configuration is done using a serial bitstream, it is easy to cascade multiple XS95 Boards to experiment with multiprocessor and multi-CPLD systems.
The XS95 is one of the prototyping boards used in Prentice Hall's new lab book on digital design, The Practical Xilinx Designer.
This book shows how to use CPLDs to build digital systems ranging from simple combinational logic up to an 8-bit microcontroller. All the examples in the book can be downloaded into the XS95 and tested.
Additional experiments and materials are presented at the XESS web site.

FPGA Devices:

Xilinx XC4010 and XC3030

Daughter card:

Xilinx XC4010 x4, or Altera MAX9000 x2, or PROTEUS (custom) x2

On-board RAM:

(Dual-Port SRAM 32Kx8) x4

External bus:

VME

Interconnect:

I-CUBE IQ320 x2

Contact:

Toshiaki Miyazaki
NTT Optical Network Systems Labs
3-1 Morinosato Wakamiya, Atsugi, 243-01, JAPAN
Email: miyazaki@nospam.aecl.ntt.co.jp
Phone: +81 462 40 2158
Fax: +81 462 40 4309

Notes:

The YARDS (Yet Another Re-definable System) is a tightly coupled FPGA/MPU system. It comprises three programmable devices, i.e., an RISC-type MPU with memories, programmable interconnect devices, and FPGAs. Using these, this system supports various styles of coupling between the FPGAs and the MPU which are suitable for constructing telecommunications functions. Using the YARDS and the ANT (ATM Network Termination) board, we implemented an Operation, Administration, and Management (OAM) operation on the Asynchronous Transfer Mode (ATM) network, and realized a remote reconfiguration function through the ATM network. See FPGA'97 proceedings for details.

FPGA Devices:

32 XC3090s

On-board RAM:

64K x 8 at each node

External bus:

Controlled by Transputer

Interconnect:

FPGAs arranged in a ring, 8-bit connections to 4 nearest neighbours' memory, 8-bit direct connections to 2 nearest neighbours. Globally controlled by transputer.

Contact:

Neil Howard
Dept. Electronics
University of York
Heslington, York YO1 5DD, UK
email: nh@nospam.ohm.york.ac.uk

Notes:

Designed and used for cellular automata applications - image morphology, local histogram equalisation, rank filtering. Neural networks also implemented.